Rules
You will find on this page the rules of the DPA contest v3.
The acquisitions shall be performed on a SASEBO-GII board using the AES design provided by the AIST (which can be downloaded from the Tools page) on the cryptographic FPGA (the Virtex 5).
Participants are free to:
- Modify the design of the control FPGA of the board (the Spartan 3)
- Use any measurement technique (power, EM...)
- Use any measurement equipment (EM probe, differential probe, oscilloscope, amplifier...)
- Use any post-processing function (noise filtering, trace resynchronization...)
Participant shall not:
- Modify the AES circuit on the cryptographic FGPA of the board