Introduction
The DPA Contest v3 is organized jointly by the National Institute of Advanced Industrial Science and Technology (AIST) and the VLSI research group from Télécom ParisTech french University.
The two first editions of the contest were attack contests (the first against DES and the second against AES), i.e. participants were asked to develop their own attacks that used traces acquired by the organizers to find the key.
However, for Side Channel Analysis, the acquisition phase of the attack is also very important. So this third edition is an acquisition contest, where participants are provided with an AES design to be loaded on the SASEBO GII board, and have to acquire their own traces.
Participants can use any measurement technique (power, EM...), tools (probes, oscilloscope...) and post-processing function (resynchronization, noise filtering...), in order to provide the best traces.
The traces acquired by the participants will be submitted to the organizers on this website and will be evaluated against several attacks using different metrics.
How to participate?
A step-by-step guide is available on the Participate page.
The submission deadline is July 31st 2012.
Latest news
- Presentation of the results during the rump session of CHES 2012: presentation (PDF)
- A press release describing the DPA contests is available on-line (in French : À l'initiative de l’Institut Télécom, les chercheurs se mobilisent contre le piratage des cartes à puces jusqu'à fin février 2012).
- You can follow the latest news from the DPA contest by following our official Twitter account or by subscribing to our announcement mailing list.
Organizers and sponsors
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Disclamer
The data and code provided by www.dpacontest.org apply to the evaluation of academic, unprotected and whitebox cryptographic implementations. The goal of this contest is definitely not to encourage piracy on whatsoever commercial hardware; instead, it aims at enhancing the state-of-the-art of ``hardware security'' against observation attacks. This approach has proved to be efficient in cryptography: the AES, the SHA-3 or the eSTREAM contests are emblematic in this respect. We wish to apply this model at the hardware level. The advances in this field also help prepare the security challenges to be met with the advent of forthcoming nano-technologies.